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ds04-21371-1e fujitsu semiconductor data sheet assp fractional-n pll frequency synthesizer mb15f83ul n n n n description the fujitsu mb15f83ul is fractional-n phase locked loop (pll) frequency synthesizer with fast lock up function. the fractional-n pll operating up to 2000 mhz and the integer pll operating up to 600 mhz are integrated on one chip. the mb15f83ul is used, as charge pump which is well-balanced output current with 1.5 ma and 6 ma selectable by serial data, direct power save control and digital lock detector. in addition, the mb15f83ul adopts a new architecture to achieve fast lock. the new package (thin bump chip carrier20) decreases a mount area of mb15f83ul more than 30 % comparing with the former b.c.c.16 (for dual pll, mb15f03sl) . the mb15f83ul is ideally suited for wireless mobile communications, such as gsm. n n n n features ? high frequency operation : rf synthesizer : 2000 mhz max. : if synthesizer : 600 mhz max. ? low power supply voltage : v cc = 2.7 v to 3.6 v ? ultra low power supply current : i cc = 5.8 ma typ. (v cc = vp = 3.0 v, ta = + 25 c, sw = 0 in if and rf locking state) (continued) n n n n packages 20-pin, plastic tssop 20-pad, plastic bcc (fpt-20p-m06) (lcc-20p-m05)
mb15f83ul 2 (continued) ? direct power saving function : power supply current in power saving mode typ. 0.1 m a (v cc = vp = 3.0 v, ta = + 25 c) , max. 10 m a (v cc = vp = 3.0 v) ? fractional function : modulo 13 fixed (implemented in rf-pll) ? dual modulus prescaler : 2000 mhz prescaler (16/17 fixed) /600 mhz prescaler (8/9 or 16/17) ? serial input programmable reference divider : rf : 7 bit (3 to 127) /if : 14 bit (3 to 16383) ? serial input programmable divider consisting of : rf section - binary 4-bit swallow counter : 0 to 15 - binary 10-bit programmable counter : 18 to 1,023 - binary 4-bit fractional counter numerator : 0 to 15 if section - binary 4-bit swallow counter : 0 to 15 - binary 11-bit programmable counter : 3 to 2,047 ? on-chip phase comparator for fast lock and low noise ? operating temperature : ta = - 40 c to + 85 c ? small package bump chip carrier.0 (3.4 mm 3.6 mm 0.6 mm) n n n n pin assignments (bcc-20) top view (lcc-20p-m05) gnd clock d oif 1 2 3 4 5 678 9 10 11 12 13 14 15 16 19 18 17 20 gnd if gnd rf v ccif vp if le fin rf fin if v ccrf ps rf ps if xfin rf xfin if osc in data ld/fout d orf vp rf (tssop-20) top view (fpt-20p-m06) osc in gnd fin if xfin if gnd if v ccif ps if vp if d oif ld/fout clock data le fin rf xfin rf gnd rf v ccrf ps rf vp rf d orf 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
mb15f83ul 3 n n n n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input pin. tcxo should be connected with an ac coupling capacitor. 220gnd ? ground pin for osc input buffer and the shift register circuit. 31fin if i prescaler input pin for the if-pll. connection to an external vco should be ac coupling. 42xfin if i prescaler complimentary input pin for the if-pll section. this pin should be grounded via a capacitor. 53gnd if ? ground pin for the if-pll section. 64v ccif ? power supply voltage input pin for the if-pll section (except for the charge pump circuit) , the shift register and the oscillator input buffer. when power is off, latched data of if-pll is lost. 75ps if i power saving mode control signal pin for the if-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps if = h; normal mode / ps if = l; power saving mode 86vp if ? power supply voltage input pin for the if-pll charge pump. 97do if o charge pump output pin for the if-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 8 ld/fout o look detect signal output (ld) /phase comparator monitoring output (fout) pins. the output signal is selected by an lds bit in a serial data. lds bit = h; outputs fout signal / lds bit = l; outputs ld signal 11 9 do rf o charge pump output pin for the rf-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 12 10 vp rf ? power supply voltage input pin for the rf-pll charge pump. 13 11 ps rf i power saving mode control pin for the rf-pll section. this pin must be set at l when the power supply is started up. (open is prohibited. ) ps rf = h; normal mode / ps rf = l; power saving mode 14 12 v ccrf ? power supply voltage input pin for the rf-pll section (except for the charge pump circuit) . 15 13 gnd rf ? ground pin for the rf-pll section. 16 14 xfin rf i prescaler complimentary input pin for the rf-pll section. this pin should be grounded via a capacitor. 17 15 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be ac coupling. 18 16 le i load enable signal input pin (with the schmitt trigger circuit.) on a rising edge of load enable, data in the shift register is transferred to the cor- responding latch according to the control bit in a serial data. 19 17 data i serial data input pin (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (if-ref counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 20 18 clock i clock input pin for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
mb15f83ul 4 n n n n block diagram 7 3 4 1 17 11 10 16 13 18 19 20 12 15 14 2 9 8 5 6 ps if fin if xfin if osc in (5) (7) (8) (9) (18) (17) (16) (11) (14) (15) (1) (2) (19) power saving if-pll prescaler (if-pll) 8/9, 16/17 4-bit latch 11-bit latch binary 14-bit pro- grammable ref. counter (if-pll) binary 11-bit programmable counter (if-pll) vcc if gnd if vp if (4) (3) (6) (10) (13) (12) (20) fp if phase comp. (if-pll) charge pump (if-pll) do if ld/fout 14-bit latch binary 4-bit swallow counter (if-pll) lds t1 t2 swc fcc csc 6-bit latch lock det. (if-pll) ld if slector ld if ld rf fr if fr rf fp if fp rf or lock det. (rf-pll) phase comp. (rf-pll) charge pump (rf-pll) do rf sc (rf-pll) sc1 sc2 vp rf gnd rf gnd vcc rf clock data le ps rf xfin rf fin rf schmitt circuit schmitt circuit schmitt circuit c n 1 c n 2 c n 3 23-bit shift register latch selector power saving rf-pll prescaler (rf-pll) 16/17 md2 binary 4-bit swallow counter (rf-pll) binary 10-bit programmable counter (rf-pll) 4-bit latch 10-bit latch md1 f 1 f 2 f 3 f 4 4-bit latch fractional counter 13 fr rf fp rf fr rf fp rf selector sc1 sc2 sfw fcf csf 5-bit latch 7-bit latch binary 7-bit pro- grammable ref. counter (rf-pll) or o : tssop 20 ( ) : bcc 20
mb15f83ul 5 n n n n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 + 4.0 v vp v cc + 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld / fout v o gnd v cc v do v do gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v v ccrf = v ccif vp v cc 3.0 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f83ul 6 * n n n n electrical characteristics (v cc = 2.7 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current i ccif *1 fin if = 480 mhz, sw c = 0 v ccif = vp if = 3.0 v 1.0 1.6 2.3 ma i ccrf *1 fin rf = 2000 mhz v ccrf = vp rf = 3.0 v 2.8 4.2 5.8 ma power saving current i psif ps = l ? 0.1 *2 10 m a i psrf ps = l ? 0.1 *2 10 m a operating frequency fin if *3 fin if if pll 100 ? 600 mhz fin rf *3 fin rf rf pll 400 ? 2000 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system - 15 ?+ 2dbm fin rf pfin rf rf pll, 50 w system - 15 ?+ 2dbm osc in v osc ? 0.5 ? v cc vp-p h level input voltage data, clock, le v ih schmitt triger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt triger input ?? 0.3 v cc - 0.4 h level input voltage ps if ps rf v ih ? 0.7 v cc ?? v l level input voltage v il ??? 0.3 v cc h level input current data, clock, le, ps if , ps rf i ih *4 ?- 1.0 ?+ 1.0 m a l level input current i il *4 ?- 1.0 ?+ 1.0 h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il *4 ?- 100 ? 0 h level output voltage ld/ fout v oh v cc = vp = 3.0 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 3.0 v, i ol = 1 ma ?? 0.4 h level output voltage do if do rf v doh v cc = vp = 3.0 v, i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 3.0 v, i dol = 0.5 ma ?? 0.4 high impedance cutoff current do if do rf i off v cc = vp = 3.0 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/ fout i oh *4 v cc = vp = 3.0 v ??- 1.0 ma l level output current i ol v cc = vp = 3.0 v 1.0 ??
mb15f83ul 7 (continued) (v cc = 2.7 v to 3.6 v, ta = - 40 c to + 85 c) *1 : conditions ; fosc = 13 mhz, ta = + 25 c in locking state. *2 : v ccif = vp if = v ccrf = vp rf = 3.0 v, fosc = 13 mhz, ta = + 25 c, in power saving mode. *3 : ac coupling. 1000 pf capacitor is connected. *4 : the symbol C (minus) means direction of current flow. *5 : v cc = vp = 3.0 v, ta = + 25 c (||i 3 | - |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 ( % ) *6 : v cc = vp = 3.0 v, ta = + 25 c [ (||i 2 | - |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 ( % ) (applied to each l dol and l doh ) *7 : v cc = vp = 3.0 v, ta = + 25 c[ (||i do (85 c) | - |i do (C40 c) ||) / 2] / [ (|i do (85 c) | + |i do (C40 c) |) / 2] 100 ( % ) (applied to each i dol and i doh ) parameter symbol condition value unit min. typ. max. h level output current do if do rf i doh *4 v cc = vp = 3.0 v v doh = vp / 2 ta = + 25 c cs bit = h - 8.2 - 6.0 - 4.1 ma cs bit = l - 2.2 - 1.5 - 0.8 ma l level output current i dol v cc = vp = 3.0 v v dol = vp / 2 ta = + 25 c cs bit = h 4.1 6.0 8.2 ma cs bit = l 0.8 1.5 2.2 ma charge pump current rate i dol /i doh i domt *5 v do = vp / 2 ? 3 ?% vs v do i dovd *6 0.5 v v do vp - 0.5 v ? 10 ?% vs ta i dota *7 - 40 c ta + 85 c, v do = vp / 2 ? 5 ?% i dol i 1 i 3 i 2 i 1 i 4 i 2 0.5 vp/2 vp - 0.5 vp i doh output voltage (v)
mb15f83ul 8 n n n n functional description 1. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sections and programmable reference dividers of if/rf-pll sections are controlled individually. serial data of binary code is entered through data pin. on a rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. note : (cn3 = 1 is pohibited) (1) serial data format the programmable reference counter for the if-pll the programmable counter and the swallow counter for the if-pll the programmable reference counter for the rf-pll the prgrammable counter and the swallow counter for the rf-pll cn1 0 1 0 1 cn2 0 0 1 1 cn3 0 0 0 0 note: data input with msb first. 1234567891011121314151617181920212223 000r c1 r c2 r c3 r c4 r c5 r c6 r c7 r c8 r c9 r c10 r c11 r c12 r c13 r c14 lds t1 t2 sw c fc c cs c 100a c1 a c2 a c3 a c4 000n c1 n c2 n c3 n c4 n c5 n c6 n c7 n c8 n c9 n c10 n c11 xx 010r f1 r f2 r f3 r f4 r f5 r f6 r f7 00000000 sc1 sc2 1fc f cs f 110a f1 a f2 a f3 a f4 0n f1 n f2 n f3 n f4 n f5 n f6 n f7 n f8 n f9 n f10 f1 f2 f3 f4 0 r c1 to r c14 : divide ratio setting bits for the reference counter of the if (3 to 16383) a c1 to a c4 : divide ratio setting bits for the swallow counter of the if (0 to 15, a < n) n c1 to n c11 : divide ratio setting bits for the programmable counter of the if (3 to 2047) lds, t1, t2 : select bits for the lock detect output or a monitoring phase comparison frequency sw c : divide ratio setting for the prescaler of the if fc c : phase control bit for the phase detector of the if cs c : charge pump current select bit of the if r f1 to r f7 : divide ratio setting bits for the reference counter of the rf (3 to 127) a f1 to a f4 : divide ratio setting bits for the swallow counter of the rf (0 to 15, a < n - 2) n f1 to n f10 : divide ratio setting bits for the programmable counter of the rf (18 to 1023) f1 to f4 : fractional-n increment setting bit for the fractional accumulator (0 to 15, f < q) sc1, sc2 : spurious cancel set bit of the rf. fc f : phase control bit for the phase detector of the rf. cs f : charge pump current select bit of the rf x : dummy bit (set 0 or 1) lsb msb direction of data shift control bit (cn3) control bit (cn2) control bit (cn1)
mb15f83ul 9 (2) data setting rf synthesizer data setting (fractional-n) the divide ratio can be calculated using the following equation : f vcorf = n total fosc ? r n total = p n + a + f / q ? (a < n - 2, f < q) binary 7 - bit programmable reference counter data setting (r f1 to r f7 ) note : divide ratio less than 3 is prohibited. fractional-n incremant of the fractional accumulator data setting ( f1 to f4 ) note : f < q f vcorf : output frequency of external voltage controlled oscillator (vco) n total : total division ratio from prescaler input to the phase detector input fosc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 7 bit reference counter (3 to 127) p : preset divide ratio of modulus prescaler (16 fixed) n : preset divide ratio of binary 10 bit programmable counter (18 to 1023) a : preset divide ratio of binary 4 bit swallow counter (0 to 15) f : a numerator of fractional-n (0 to 15) q : a denominator of fractional-n, modulo 13 divide ratio (r) r f7 r f6 r f5 r f4 r f3 r f2 r f1 3 0000011 4 0000100 ? ??????? 52 0110100 ? ??????? 127 1111111 setting value(f) f4 f3 f2 f1 0 0000 1 0001 2 0010 ? ???? 15 1111
mb15f83ul 10 binary 10 - bit programable counter data setting ( n f1 to n f10 ) note : divide ratio less than 18 is prohibited. binary 4-bit swallow counter data setting (a f1 to a f4 ) note : a < n - 2 spurious cancel bit setting note : the bits set how much the amount of spurious cancel. if the large is selected, a spurious is tended to become small. phase comparator phase switching data setting notes : z = high-z depending upon the vco and lpf polarity, fc bit should be set. charge pump current select bit setting divide ratio (n) n f10 n f9 n f8 n f7 n f6 n f5 n f4 n f3 n f2 n f1 18 0000010010 19 0000010011 ? ?????????? 32 0000100000 ? ?????????? 1023 1 1 1 1 1 1 1 1 1 1 divide ratio (a) a f4 a f3 a f2 a f1 00000 10001 20010 ? ???? 15 1111 spurious cancel amount sc1 sc2 large 0 0 midium 0 1 small 1 0 fc f = = = = high fc f = = = = low d o d o fr > fp h l fr = fp z z fr < fp l h vco polarity 1 2 cs f current value 1 6.0 ma 0 1.5 ma
mb15f83ul 11 if synthesizer data setting (integer) the divide ratio can be calculated using the following equation : f vcoif = [ (p n) + a] fosc ? r (a < n) binary 14-bit programmable reference counter data setting (r c1 to r c14 ) note : divide ratio less than 3 is prohibited. binary 11-bit programmable counter data setting (n c1 to n c11 ) note : divide ratio less than 3 is prohibited. binary 4-bit swallow counter data setting (a c1 to a c4 ) note : a < n prescaler data setting (sw c ) divide ratio (r) r c14 r c13 r c12 r c11 r c10 r c9 r c8 r c7 r c6 r c5 r c4 r c3 r c2 r c1 3 00000000000011 4 00000000000100 ? ?????????????? 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 divide ratio (n) n c11 n c10 n c9 n c8 n c7 n c6 n c5 n c4 n c3 n c2 n c1 3 00000000011 4 00000000100 ? ??????????? 2047 11111111111 divide ratio (a) a c4 a c3 a c2 a c1 0 0000 1 0001 2 0010 ? ???? 15 1111 sw c prescaler divide ratio 18/9 0 16/17 f vcoif : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of modulus prescaler (8 or 16) n : preset divide ratio of binary 11 bit programmable counter (3 to 2047) a : preset divide ratio of binary 4 bit swallow counter (0 to 15) fosc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14 bit reference counter (3 to 16383)
mb15f83ul 12 phase comparator phase switching data setting notes : z = high-z depending upon the vco and lpf polarity, fc bit should be set. charge pump current select data setting (cs c ) common setting ld/fout output select data setting fc bit setting when designing a synthesizer, the fc bit setting depends on the vco and lpf characteristics. fc c = = = = high fc c = = = = low d o d o fr > fp h l fr = fp z z fr < fp l h cs c do current 1 6.0 ma 0 1.5 ma ld/fout lds t1 t2 ld output 0 ?? fout output fr if 100 fr rf 110 fp if 101 fp rf 111 (1) (2) high max. when the lpf and vco characteristics are similar to (1) , set fc bit h. when the vco characteristics are similar to (2) , set fc bit l. vco output frequency lpf output voltage
mb15f83ul 13 2. power saving mode (intermittent mode control) ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters the power saving mode, reducing the current consumption. see n electrical characteristics for the specific value. the phase detector output, do, becomes high impedance. for the single pll, the lock detector, ld, remains high, indicating a locked condition. for the dual pll, the lock detector, ld, is shown in n phase detector output waveform the ld output logic table. setting the ps pin high releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes: when power (v cc ) is first applied, the device must be in standby mode and ps = low, for at least 1 m s. ps pin must be set l for power on. ps pin status h normal mode l power saving mode on off v cc clock data le ps (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps = l (power saving mode) at power on (2) set serial data 1 m s after power supply remains stable (v cc 3 2.2 v) . (3) release power saving mode (ps : l ? h) 100 ns after setting serial data.
mb15f83ul 14 3. serial data input timing lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data on the rising edge of the clock, one bit of data is transferred into shift register. note : le should be l when the data is transferred into the shift register. parameter min. typ. max. unit parameter min. typ. max. unit t 1 20 ?? ns t 5 100 ?? ns t 2 20 ?? ns t 6 20 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 30 ?? ns
mb15f83ul 15 n n n n phase detector output waveform ld output logic table if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l fr if/rf fp if/rf ld d oif/rf t wu t wl d oif/rf (fc bit = high) (fc bit = low) z h l z h l notes: phase error detection range = - 2 p to + 2 p pulses on do if/rf signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu 3 2/fosc [ s ] : i.e. t wu 3 153.8 ns when fosc = 13.0 mhz t wu 4/fosc [ s ] : i.e. t wl 307.7 ns when fosc = 13.0 mhz
mb15f83ul 16 n n n n test circuit (for measuring input sensitivity fin/osc in ) mb15f83ul s.g p.g s.g fout oscilloscope 1000 pf 50 w vp if v ccif 0.1 m f 0.1 m f 1000 pf 1000 pf 50 w ld/fout d orf vp rf ps rf v ccrf gnd rf xfin rf fin rf le data clock d oif vp if ps if v ccif gnd if xfin if fin if gnd osc in controller (divide ratio setting) 1000 pf 50 w 1000 pf vp rf v ccrf 0.1 m f 0.1 m f 11 12 13 14 15 16 17 18 19 20 10987654321 note : tssop-20
mb15f83ul 17 n n n n typical characteristics 1. fin input sensitivity rf-pll input sensitivity vs. input frequency fin rf (mhz) pfin rf (dbm) if-pll input sensitivity vs. input frequency fin if (mhz) pfin if (dbm) spec 0 500 1000 1500 2000 2500 10 0 - 10 - 20 - 30 - 40 - 50 2.7 v 3.0 v 3.6 v spec 3.3 v ta = + 25 c spec 0 500 1000 1500 2000 10 0 - 10 - 20 - 30 - 40 - 50 2.7 v 3.0 v 3.3 v 3.6 v ta = + 25 c
mb15f83ul 18 2. osc in input sensitivity 0 50 100 150 200 250 300 10 0 - 10 - 20 - 30 - 40 - 50 - 60 v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec ta = + 25 c spec input sensitivity vs. input frequency input frequency f osc (mhz) input sensitivity v osc (dbm)
mb15f83ul 19 3. rf-pll do output current 20 - 20 0 0123 ? 1.5 ma mode ? 6.0 ma mode 20 - 20 0 0123 charge pump output current i do (ma) i do - v do charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v)
mb15f83ul 20 4. if-pll do output current ? 1.5 ma mode ? 6.0 ma mode i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) 10.0 - 10.0 v cc = vp = 2.7 v 0 0.0 1.0 2.0 3.0 v cc = vp = 2.7 v 10.0 0 - 10.0 0.0 1.0 2.0 3.0
mb15f83ul 21 5. fin input impedance 45.859 w - 188.77 w 1 ghz 25.48 w - 103.67 w 1.7 ghz 22.152 w - 83.391 w 2 ghz 1 : 2 : 3 : start 1 000.000 000 mhz stop 2 600.000 000 mhz 1.1765 pf 1 3 2 325.78 w - 732.22 w 100 mhz 21.516 w - 170.72 w 500 mhz 12.422 w - 108.38 w 750 mhz 1 : 2 : 3 : start .030 000 mhz stop 1 000.000 000 mhz 4 : 9.3437 w- 75.625 w 2.1045 pf 1 000.000 000 mhz 1 3 2 4 fin r input impedance fin if input impedance
mb15f83ul 22 6. osc in input impedance 28.625 w - 667.75 w 100 mhz 2.1273 k w - 5.9445 k w 10 mhz 2.1273 k w - 5.9445 k w 10 mhz 1 : 2 : 3 : start .030 000 mhz stop 100.000 000 mhz 4 : 092.56 w -1.3177 k w 2.4157 pf 50.000 000 mhz 1 3 2 4 3 osc in input impedance
mb15f83ul 23 n n n n reference information ( for lock - up time , phase noise and reference leakage ) s.g. osc in fin vco d o lpf test circuit spectrum analyzer 3.0 k w 3900 pf 10 k w 390 pf 82 pf f vco = 1733 mhz v cc = 3.0 v k v = 44 mhz/v v vco = 3.5 v fr = 200 khz ta = + 25 c f osc = 13 mhz cp : 6 ma mode lpf qm = 13 ? pll reference leakage ? pll phase noise atten 10 db rl 0 dbm center 1.733000 ghz rbw 10 khz vbw 10 khz span 1.000 mhz swp 50.0 ms d mkr - 69.00 db 200 khz vavg 100 10 db/ d mkr 200 khz - 69.00 db d atten 10 db rl 0 dbm center 1.73299933 ghz rbw 100 hz vbw 100 hz span 10.00 khz swp 802 ms d mkr - 63.17 db 1.00 khz vavg 24 10 db/ d mkr 1.00 khz - 63.17 db d
mb15f83ul 24 pll lock up time 1733 mhz ? 1803 mhz within 1 khz lch ? hch 189 m s pll lock up time 1803 mhz ? 1733 mhz within 1 khz hch ? lch 167 m s 1.733004500 gh z 1.733000500 gh z 1.732996500 gh z - 956 m s 1.544 ms 500.0 m s/div 4.044 ms 1.803004500 gh z 1.803000500 gh z 1.802996500 gh z - 956 m s 1.544 ms 500.0 m s/div 4.044 ms
mb15f83ul 25 n n n n application example 0.1 m f 18 17 20 19 16 15 14 13 12 11 34 12 5678910 1000 pf 1000 pf output 3.0 v mb15f83ul 1000 pf 1000 pf 1000 pf 3.0 v 0.1 m f 0.1 m f output lock det. vco lpf vco lpf tcxo d orf ps rf vp rf xfin rf gnd rf v ccrf fin rf le data clock d oif ps if vp if ld/fout v ccif fin if xfin if gnd if osc in gnd 3.0 v 0.1 m f 3.0 v from controller notes: schmit trigger circuit is provided (insert a pull-up or pull-down resistor to prevent oscillation when open-circuited in the input) . tssop-20
mb15f83ul 26 n n n n usage precautions (1) v ccrf , vp rf , v ccif and vp if must be equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v ccrf , vp rf , v ccif and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions : -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n n n n ordering information part number package remarks mb15f83ulpft 20-pin plastic tssop (fpt-20p-m06) mb15f83ulpva 20-pad plastic bcc (lcc-20p-m05)
mb15f83ul 27 n n n n package dimensions (continued) 20-pin plastic tssop (fpt-20p-m06) * : these dimensions do not include resin protrusion. dimensions in mm ( inches ) c 1999 fujitsu limited f20026s-2c-2 6.50?.10(.256?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 10 20 11 "a" 0.17?.05 (.007?002) m 0.13(.005) details of "a" part 0~8 (.018/.030) 0.45/0.75 (0.50(.020)) 0.25(.010) (.041?002) 1.05?.05 (mounting height) 0.07 +0.03 ?.07 +.001 ?003 .003 (stand off) lead no. index
mb15f83ul 28 (continued) 20-pad plastic bcc (lcc-20p-m05) dimensions in mm ( inches ) c 2001 fujitsu limited c20056s-c-2-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.55?.05 0.075?.025 (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) (.003?001) (mounting height) (.022?002)
mb15f83ul fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0107 ? fujitsu limited printed in japan

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